The present invention generally relates to integrated circuits (ICs). More particularly, the present invention relates to ICs incorporating dynamic or domino logic circuits.
A static CMOS gate is a fully complementary logic gate (with P and N devices configured to implement a desired logic function). A dynamic CMOS gate consists of an N-device logic structure having an output node pre-charged to Vcc with a single clocked PMOS device and being conditionally discharged (evaluated) by a set of n-devices connected to Vss.
The clocked PMOS device has a gate connected to an input clock signal. When the clock input is active, the output node is xe2x80x9cprechargedxe2x80x9d through the PMOS device to Vcc. When the clock input is inactive, the output node is conditionally discharged (evaluated) through the N-devices to Vss. The set of N-devices implement the logic function.
Dynamic or domino logic units are referred to as being xe2x80x9cdynamicxe2x80x9d because operation of the unit is controlled dynamically by the input clock signal. The logic units are typically arranged in a plurality of stages, each having logic cells such as NAND gates, NOR gates, etc., with each stage separated by an inverting stage. With this arrangement, input signals applied to the first stage while the clock signal is active trigger operation of the remaining stages in sequence yielding a domino-like signal propagation effect within the logic unitxe2x80x94hence, the alternative name xe2x80x9cdominoxe2x80x9d circuit.
One of the requirements for correct operation is that during the evaluate phase, the inputs to the N-device can only change from a non-active to an active state. Otherwise, the output could be corrupted, and there is no set of PMOS devices to pull it back up.
In use, dynamic or domino logic units operate in two phasesxe2x80x94a pre-charge phase and an evaluate phase. During the pre-charge phase, logic cells of the domino circuit are pre-charged. During the evaluate phase, input signals are applied to the inputs of each of the logic cells and the clock signal is activated. Depending upon the inputs, some of the logic cells of the domino circuit may need to discharge to pull the output line of the logic cell from high to low, thereby sinking current from the power supply.
A disadvantage of domino logic circuits, however, is that leakage currents may flow through the n-type transistors even when the n-type transistors should be off. Thus, a high value at the dynamic output may be pulled down to low, causing loss of data.
One approach to compensating for the leakage current is to use a keeper circuit. A typical keeper circuit, called a half keeper, includes an inverter and a p-type transistor. The inverter includes an input and an output. The input of the inverter is coupled to the dynamic output of the domino logic circuit and the output of the inverter is coupled to an output, which may be connected to the next domino stage and to the gate of the p-type transistor. The source of the p-type transistor is coupled to a positive power supply voltage Vcc and the drain of the p-type transistor is coupled to the dynamic output of the domino logic circuit. Thus, when the dynamic output of the domino logic circuit is high, the p-type transistor of the keeper circuit will be on, further charging the dynamic output of the domino logic circuit to high.
However, the electrical behavior of the MOS transistors is dramatically changing with progress in device scaling. Particularly, the sub-threshold currents, which are exponentially increasing, result in significant increase of power consumption and large leakage current. The increasing leakage currents are severely limiting to performance, robustness, and consequently practical use of domino circuits. Leakage currents are predominantly critical to wide Domino gates with many parallel pull-down transistors, such as wide xe2x80x9cORxe2x80x9d gates. This class of domino gates often generates fewer logic levels, which in turn can result in compact, high-performance, and relatively low power circuits, useful in design of memory, control, and wide arithmetic units.
Stronger p-type transistors are required in keeper circuits to compensate for the larger leakage currents in domino logic circuits. However, a stronger p-transistor (keeper) increases the contention at the dynamic output, and this degrades the performance of the domino circuits. The gain of the traditional keeper is bounded and must be low enough to allow the pull-down network to complete a potential High-to-Low transition. The gate output transition time is dependent on the gain ratio of the keeper and the weakest pull-down branch, as both the charge in the storage capacitance and additional charge, initially supplied by the keeper, must be drained out during a High-to-Low transition.
Thus, a stronger keeper increases the delay of the domino gate, and the conventional solution involves a trade-off between robustness and performance, and shows difficulty in handling relatively large leakage in wide domino stages created by low threshold voltage sub-micron devices. This shortcoming becomes even more critical for medium and low frequency operations.